Some technical clipping questions about Class D amplifiers

[enzowho 10+ year member]

I was thinking about this last night as I was walking home from the lab, so somebody help me out. First, let me make sure this is all right:

A class D amp takes the signal, compares it using a pulse width modulator (PWM) then eventually sends the square wave signal to the gates of a power CMOS pair. On an un-bridged configuration, the MOSFET's see either the supply voltage or the negative supply voltage (after it has been bumped up by the x-former). The voltage drop across the load/MOSFET's is always going to be the same for any volume level. The current though is determined by the applied gate voltage.

Now, what happens if you drive your class D amplifier into severe clipping. The MOSFET's cannot see any voltage above the supply voltage, but they can draw more current from this supply. Does this mean then that if your amplifier doesn't have over-current protection (or something of that nature) it would simply draw too much current and destroy the MOSFET's?

Second question. How does a Class D amplifier clip anyways? If its output is a square wave at all volume levels, how can you overdrive it and make a "harsher" square wave?

Thanks for all the help!

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[Thnking 10+ year member]

I was thinking about this last night as I was walking home from the lab, so somebody help me out. First, let me make sure this is all right:
A class D amp takes the signal, compares it using a pulse width modulator (PWM) then eventually sends the square wave signal to the gates of a power CMOS pair. On an un-bridged configuration, the MOSFET's see either the supply voltage or the negative supply voltage (after it has been bumped up by the x-former). The voltage drop across the load/MOSFET's is always going to be the same for any volume level. The current though is determined by the applied gate voltage.

Not necessarily the correct path, but it seems you have the basic idea. You can’t say the Vdrop will be the same for any output, but I think you mean the amplifier gives a fixed amount of power into a given load for a specific period.

Now, what happens if you drive your class D amplifier into severe clipping. The MOSFET's cannot see any voltage above the supply voltage, but they can draw more current from this supply. Does this mean then that if your amplifier doesn't have over-current protection (or something of that nature) it would simply draw too much current and destroy the MOSFET's?

The load can cause the VA to exceed a MOSFET’s thermal in any topology with clipping without a protection circuit.

Second question. How does a Class D amplifier clip anyways? If its output is a square wave at all volume levels, how can you overdrive it and make a "harsher" square wave?

Thanks for all the help!

The max rail voltage isn’t exceeded in any topology, the difference in clipping with a class D is the period (or duty cycle) of the PWM waveform is increased to create a clipped waveform after the output filter.

In other words the OPS PWM waveform has an increased duty cycle. As it’s filtered to the “musical” waveform, due to the increased waveform period, the resultant waveform is clipped or distorted/increased amplitude.

Hope that helps

Grant

 

[thch 10+ year member]

I was thinking about this last night as I was walking home from the lab, so somebody help me out. First, let me make sure this is all right:
A class D amp takes the signal, compares it using a pulse width modulator (PWM) then eventually sends the square wave signal to the gates of a power CMOS pair. On an un-bridged configuration, the MOSFET's see either the supply voltage or the negative supply voltage (after it has been bumped up by the x-former). The voltage drop across the load/MOSFET's is always going to be the same for any volume level. The current though is determined by the applied gate voltage.

not usually true. power class D amps usually are NMOS only, though CMOS and PMOS versions exist. (FYI, for NMOS amps, a portion of the load energy gets pumped into a capacitor to allow the upper FET to turn on.) current demand is based upon the load, and the amount of time the devices stay on vs off. practical designs require both FETs be off for a brief time, in this case, any current flowing in the inductive speaker will flow through the FET's "body diode".

thus the output, before filtering, is either +Vdd, 0V, or -Vss. after the output filter, it can be any level in between.**

Now, what happens if you drive your class D amplifier into severe clipping. The MOSFET's cannot see any voltage above the supply voltage, but they can draw more current from this supply. Does this mean then that if your amplifier doesn't have over-current protection (or something of that nature) it would simply draw too much current and destroy the MOSFET's?

it is not noramlly desired to operate with a duty cycle of greater then 80%. this is due to the need to prevent both devices from conducting at the same time. as such, many class D amps have "overmodulation limiting", which limits the duty ratio. failing that, you would just have a FET which is on for a prolonged period of time, and the amp would have clipping in a similar manner as a class B amplifier. if the output current is allowed to rise, the power dissipated by the device may grow higher then intended. this is especially true if the applied Vgs cannot keep the device from saturating*. when this happens, the voltage across the device increases, and you get the FET to burn up (since it was handeling a high current as well)

Second question. How does a Class D amplifier clip anyways? If its output is a square wave at all volume levels, how can you overdrive it and make a "harsher" square wave?

class D is actually a wide range of implementations. in the case of overmodulation protected amplifiers, the maximum error signal is limited, either with a hard limit or a soft one. this prevents the amp from wanting to put out even its maximum rail voltage.

*FETs "saturate" when the current through them cannot increase without changing Vgs. this is backwards from a BJT which "saturates" when the voltage across the device cannot become lower.

** and technically, the voltage before the filter will be clamped a little bit above the supply voltage when both FETs are off and current is flowing in the flyback path made by one of the FET's "body diodes"

 

[jrouter76 10+ year member]

not usually true. power class D amps usually are NMOS only, though CMOS and PMOS versions exist. (FYI, for NMOS amps, a portion of the load energy gets pumped into a capacitor to allow the upper FET to turn on.) current demand is based upon the load, and the amount of time the devices stay on vs off. practical designs require both FETs be off for a brief time, in this case, any current flowing in the inductive speaker will flow through the FET's "body diode".
thus the output, before filtering, is either +Vdd, 0V, or -Vss. after the output filter, it can be any level in between.**

it is not noramlly desired to operate with a duty cycle of greater then 80%. this is due to the need to prevent both devices from conducting at the same time. as such, many class D amps have "overmodulation limiting", which limits the duty ratio. failing that, you would just have a FET which is on for a prolonged period of time, and the amp would have clipping in a similar manner as a class B amplifier. if the output current is allowed to rise, the power dissipated by the device may grow higher then intended. this is especially true if the applied Vgs cannot keep the device from saturating*. when this happens, the voltage across the device increases, and you get the FET to burn up (since it was handeling a high current as well)

class D is actually a wide range of implementations. in the case of overmodulation protected amplifiers, the maximum error signal is limited, either with a hard limit or a soft one. this prevents the amp from wanting to put out even its maximum rail voltage.

*FETs "saturate" when the current through them cannot increase without changing Vgs. this is backwards from a BJT which "saturates" when the voltage across the device cannot become lower.

** and technically, the voltage before the filter will be clamped a little bit above the supply voltage when both FETs are off and current is flowing in the flyback path made by one of the FET's "body diodes"

awsome info,you ouight to be teaching electronics on the side to us .

 

[thch 10+ year member]

i wouldn't mind that. I got into electrical engineering through car audio. It was a choice between electrical engineering, and computer science/engineering. I'm not bad at either, but I am employed as an electrical engineer.

one of the reasons I frequent car audio forums is to encourage people to learn more and more about engineering. A lack of formal training doens't mean you can't learn on your own! At school and work I am respected for my wide range of knowledge (i have interest other then audio as well), much of which was not gathered in a classroom!

 

[enzowho 10+ year member]

not usually true. power class D amps usually are NMOS only, though CMOS and PMOS versions exist. (FYI, for NMOS amps, a portion of the load energy gets pumped into a capacitor to allow the upper FET to turn on.) current demand is based upon the load, and the amount of time the devices stay on vs off. practical designs require both FETs be off for a brief time, in this case, any current flowing in the inductive speaker will flow through the FET's "body diode". thus the output, before filtering, is either +Vdd, 0V, or -Vss. after the output filter, it can be any level in between.**

Okay, when I was thinking of the CMOS pair, I was thinking along the lines of a basic inverter circuit, driven by a single output driver. Anyways, everything you said there made sense. Also, now that you got me thinking more indepth about this, the coil's inductance could probably be used as part of the output filter design huh?

it is not noramlly desired to operate with a duty cycle of greater then 80%. this is due to the need to prevent both devices from conducting at the same time. as such, many class D amps have "overmodulation limiting", which limits the duty ratio. failing that, you would just have a FET which is on for a prolonged period of time, and the amp would have clipping in a similar manner as a class B amplifier. if the output current is allowed to rise, the power dissipated by the device may grow higher then intended. this is especially true if the applied Vgs cannot keep the device from saturating*. when this happens, the voltage across the device increases, and you get the FET to burn up (since it was handeling a high current as well)

Okay, so I did a little research into this to better understand how the PWM works and how the signal was processed. So when you refer to the duty cycle, you are basically talking about the % of time the signal voltage is greater then the the reference sawtoothing wavform during its positive half cycle voltage, and less then the sawtooth waveform during the negative half cycle. (I dont quite know how comparitors work, so if you have any articles where I can learn more please give me a link).

Now, here is where I don't quite understand...(let's assume there are no protection circuits in the design) If the signal (the analog one from your cd player) is greater then the reference sawtooth waveform, then the (say top) MOSFET would remain on for a longer duration then intended (also, we just threw the Nyquist freq. out the door I think...lol). Once the negative half cycle of the sawtooth waveform kicks in, the lower MOSFET would conduct, which would create a short circuit between V_dd and -V_dd. (re-reading that, I really don't think that's right. It seems more like both fet's would turn off...hmmm)

Okay, so when you refer to the output current being allowed to rise, are you refereing to a situation where the load resistance is too low? That situation makes sense to me, because too much current is sourced, the transistor falls into the triode region and poof. Is there any other way this could happen through from clipping?

 

[thch 10+ year member]

Okay, when I was thinking of the CMOS pair, I was thinking along the lines of a basic inverter circuit, driven by a single output driver. Anyways, everything you said there made sense. Also, now that you got me thinking more indepth about this, the coil's inductance could probably be used as part of the output filter design huh?

IIRC, some of the smaller class D amps do this "filterless" design. this is seen in some cell phones, as there is no room for a 1W loss.

in filtered designs, the speaker loads a passive filter, which makes class D designs interesting. the filtering also makes feedback interesting, and leads to a type of estimation of output being used instead.

Okay, so I did a little research into this to better understand how the PWM works and how the signal was processed. So when you refer to the duty cycle, you are basically talking about the % of time the signal voltage is greater then the the reference sawtoothing wavform during its positive half cycle voltage, and less then the sawtooth waveform during the negative half cycle. (I dont quite know how comparitors work, so if you have any articles where I can learn more please give me a link).

yes, comparison with a triangle wave is one classic way to implement class D. keep in mind that its not the _ONLY_ way to do it though. a PWM waveform will go high, then low. the duty cycle refers to the percentage of "on" time vs total time. when comparing to a triangle wave, increaseing the reference signal (the audio) causes duty cycle to vary in a linear fashion.

analog compare is a simple 1 bit ADC -- if V+ > V- , Vout = +. if V+

comparator IC implementations are a bit different, as it is common to have "open collector" outputs, which aren't related to the topic at hand.

see also "sigma delta", which is a more digital way of doing class D, but has subtle limitations.

Now, here is where I don't quite understand...(let's assume there are no protection circuits in the design) If the signal (the analog one from your cd player) is greater then the reference sawtooth waveform, then the (say top) MOSFET would remain on for a longer duration then intended (also, we just threw the Nyquist freq. out the door I think...lol). Once the negative half cycle of the sawtooth waveform kicks in, the lower MOSFET would conduct, which would create a short circuit between V_dd and -V_dd. (re-reading that, I really don't think that's right. It seems more like both fet's would turn off...hmmm)

as you move the audio input to higher voltages, the duty cycle increases towards 100%. once the input is higher then the peaks on the triangle wave, the duty ratio stays at 100% -- there is no way to make the FET be on for longer then the total amount of time!

as with any amplifier, the system dynamics have changed -- the amp has lost some control.

as the wave form moves back down, the duty cycle returns to something less the 100%. as the amp hits the negative rail, the duty cycle will reach 0%.

as for nyquist, at this point you can only produce DC. so sampling isn't much of a concern. (looking only at the time during clipping. a clipped wave is still rich in AC components when viewed overall. this apparent difference is a well known mathmatical issue when comparing time to frequency.)

Okay, so when you refer to the output current being allowed to rise, are you refereing to a situation where the load resistance is too low? That situation makes sense to me, because too much current is sourced, the transistor falls into the triode region and poof. Is there any other way this could happen through from clipping?

originally the FET only sourced current for 80% of its cycle. it must be able to do so for 100% of its cycle. really, i'm not overly worried about FETS that stay on -- they can usually source ample currents well in excess of what's needed. but if the FET moves towards saturation, very bad things happen.

edit -- for switching power supplies (similar to class D), FETs normally can't be on for 100% duty cycle because the magnetic transformer/inductor will saturate and allow current to skyrocket.

 

[luvinthebass 5,000+ posts]

Class D amps are awesome for subs, they are about 70-80% efficient at 1/3 power compared to an Class A/B amp that is 25% at that power and right before clippin the Class D is around 80-90% and the Class A/B is around 50-60% i love my Kicker Class D 600.1 amp //content.invisioncic.com/y282845/emoticons/biggrin.gif.d71a5d36fcbab170f2364c9f2e3946cb.gif never gets hot

 

[ssj2xxgotenxx 10+ year member]

//content.invisioncic.com/y282845/emoticons/confused.gif.e820e0216602db4765798ac39d28caa9.gif //content.invisioncic.com/y282845/emoticons/confused.gif.e820e0216602db4765798ac39d28caa9.gif //content.invisioncic.com/y282845/emoticons/confused.gif.e820e0216602db4765798ac39d28caa9.gif //content.invisioncic.com/y282845/emoticons/confused.gif.e820e0216602db4765798ac39d28caa9.gif

 

[enzowho 10+ year member]

originally the FET only sourced current for 80% of its cycle. it must be able to do so for 100% of its cycle. really, i'm not overly worried about FETS that stay on -- they can usually source ample currents well in excess of what's needed. but if the FET moves towards saturation, very bad things happen.

Perhaps there is something I have missed. I thought you wanted one of your FET's to be in saturation and the other to be off. That way the circuit would appear to have a short circuit to either the positive or negative rail voltage. It seems if one was operated in the triode region it would dissipate too much power and burn.

Alright let me check to see if I understand everything. A class A/B amplifier will clip when the signal into the base is too large and causes the V_o to hit the rail voltage and "flat-top" for part of the waveform. A class-D amplifier will clip when the signal voltage is larger then the PWM waveform. The output signal from the PWM circuitry would elongate the square wave output and keep one of the FET's on for an extended period of time. As the output rectangular wave increases its period, the frequency decreases to the place where the ouput filters cannot filter the waveform.

I do have another question (sorry). Lets say we input an overly large signal that clips in the PWM circuitry. In practical applications, do we ever see this signal elongate to the place where it can still be filtered to produce a much lower frequency? Basically 100Hz input signal -> compared with pwm -> square wave with T_s = 10*input signal -> output filters -> 10 Hz signal at subwoofer.

Thank you very much for your help. It would be awesome if you could randomly create some technical threads. Also, just out of curiosity where do you work?

 

[thch 10+ year member]

Perhaps there is something I have missed. I thought you wanted one of your FET's to be in saturation and the other to be off. That way the circuit would appear to have a short circuit to either the positive or negative rail voltage. It seems if one was operated in the triode region it would dissipate too much power and burn.

as i've said, the physists who came up with FETs messed up the terms. "saturated" fets mean the current is limited (and changing Vds will not affect this), not that the voltage across the device is minimized.

Alright let me check to see if I understand everything. A class A/B amplifier will clip when the signal into the base is too large and causes the V_o to hit the rail voltage and "flat-top" for part of the waveform. A class-D amplifier will clip when the signal voltage is larger then the PWM waveform. The output signal from the PWM circuitry would elongate the square wave output and keep one of the FET's on for an extended period of time. As the output rectangular wave increases its period, the frequency decreases to the place where the ouput filters cannot filter the waveform.

in a class AB amp, the amp will try to produce the waveform as much as possible. but there is usually some limitation, which occurs in the manner you describe.

as for class D, the PWM wave is commonly a fixed frequency signal (fixed period really) in which the on/off times are varied in order to perform a simple analog multiply (it acts as a mixer). this method generates a lot of high frequency compoentents (its basically a mixer), and a filter is used to give a good output.

if you allow a 100% duty cycle (one device always on), current can increase.

in both the class D and class AB cases, you hit a limit after which the amp can't really control the speaker.

I do have another question (sorry). Lets say we input an overly large signal that clips in the PWM circuitry. In practical applications, do we ever see this signal elongate to the place where it can still be filtered to produce a much lower frequency? Basically 100Hz input signal -> compared with pwm -> square wave with T_s = 10*input signal -> output filters -> 10 Hz signal at subwoofer.

this is where overmodulation protection is involved. before the output stage, there will be some linear (class A or AB) amplifier that does the basic signal processing. a limiter can be applied here.

keep in mind that class D is not actually "sampled". the triangle wave is constant frequency, and the outputs are discrete, but the timing between transitions is based upon the analog compare. This is how classic Class D is differenent from sigma-delta implementations. sampling is actually the dual of class D -- the output level can be anything, but the time intervals are discrete. and in many implementations, like ADC, is done with sampling, giving a discrete level and discrete interval.

Thank you very much for your help. It would be awesome if you could randomly create some technical threads. Also, just out of curiosity where do you work?

I sometimes do, but they die out. I'm not sure I can say where specifically I work (need to read contract). I work for a company that builds some large power stages for industrial applications (nothing that a consumer would use). We also do some control/protection for these applications.

 

[enzowho 10+ year member]

as i've said, the physists who came up with FETs messed up the terms. "saturated" fets mean the current is limited (and changing Vds will not affect this), not that the voltage across the device is minimized.

True now that I think about it for a while; I just didn't put all the pieces together before. For some reason I really thought several of my electronics profs discussed using FET's as switches. Open-circuits when they are in cut-off and shorts in saturation...hmm... Missed something I guess:crap:

Well, I think that's about all the questions I have for the moment. I'm sure as I continue to learn more in my degree I will be back for more answers. Thanks for your time and patience!